Boundary word line voltage shift

ABSTRACT

Apparatuses, systems, methods, and computer program products for dynamically determining boundary word line voltage shift are presented. An apparatus includes an array of non-volatile memory cells and a controller. A controller includes a trigger detection component that is configured to detect a trigger condition associated with a last programmed word line of a partially programmed erase block of an array of non-volatile memory cells. A controller includes a voltage component that is configured to determine a read voltage threshold for a last programmed word line of a partially programmed erase block in response to a trigger condition. A controller includes a voltage shift component that is configured to calculate, dynamically, a read voltage threshold shift for a last programmed word line based on a determined read voltage threshold for the last programmed word line and a baseline read voltage threshold.

TECHNICAL FIELD

The present disclosure, in various embodiments, relates to computerstorage devices and more particularly relates to dynamically determininga voltage shift of a boundary word line of a partially programmed eraseblock.

BACKGROUND

Memory devices may be organized into erase blocks or arrays of memoryelements. Erase blocks may further be organized into pages, which arethe smallest programmable unit physically made up of a row of cellslinked on the same word line. Erase blocks may be partially programmedsuch that a programmed word line may be adjacent to an unprogrammed wordline. The programmed word line may be known as a boundary word line. Theboundary word line may have different characteristics than otherprogrammed word lines, and therefore may have a different optimal readvoltage threshold. A fixed read voltage threshold or a fixed readvoltage threshold shift from a baseline read voltage threshold may beused for boundary word lines; however, the optimal read voltagethreshold for the boundary word line may change over time due todifferent conditions or states of the boundary word line, making thefixed voltage threshold shifts ineffective.

SUMMARY

Various embodiments are disclosed, including apparatuses, systems,methods, and computer program products for dynamically determiningboundary word line voltage shift. In one embodiment, an apparatusincludes an array of non-volatile memory cells and a controller. Acontroller, in certain embodiments, includes a trigger detectioncomponent that is configured to detect a trigger condition associatedwith a last programmed word line of a partially programmed erase blockof an array of non-volatile memory cells. A controller, in someembodiments, includes a voltage component that is configured todetermine a read voltage threshold for a last programmed word line of apartially programmed erase block in response to a trigger condition. Acontroller, in a further embodiment, includes a voltage shift componentthat is configured to calculate, dynamically, a read voltage thresholdshift for a last programmed word line based on a determined read voltagethreshold for the last programmed word line and a baseline read voltagethreshold.

A method, in one embodiment, includes detecting a trigger conditionassociated with a last programmed word line of a partially programmederase block of an array of non-volatile memory cells. A method, infurther embodiments, includes determining a read voltage threshold for alast programmed word line of a partially programmed erase block inresponse to a trigger condition. A method, in some embodiments, includescalculating, dynamically, a read voltage threshold shift for a lastprogrammed word line based on a determined read voltage threshold forthe last programmed word line and a baseline read voltage threshold. Incertain embodiments, a method includes reading data from a lastprogrammed word line using a determined read voltage threshold based ona read voltage threshold shift.

An apparatus, in one embodiment, includes means for detecting a triggercondition associated with a last programmed word line of a partiallyprogrammed erase block of an array of non-volatile memory cell. Anapparatus, in further embodiments, includes means for determining a readvoltage threshold for a last programmed word line of a partiallyprogrammed erase block in response to a trigger condition. An apparatus,in certain embodiments, includes mean for calculating, dynamically, aread voltage threshold shift for a last programmed word line based on adetermined read voltage threshold for the last programmed word line anda baseline read voltage threshold. In one embodiment, an apparatusincludes means for reading data from a last programmed word line basedon a read voltage threshold shift for the last programmed word line.

BRIEF DESCRIPTION OF THE DRAWINGS

A more particular description is included below with reference tospecific embodiments illustrated in the appended drawings. Understandingthat these drawings depict only certain embodiments of the disclosureand are not therefore to be considered to be limiting of its scope, thedisclosure is described and explained with additional specificity anddetail through the use of the accompanying drawings, in which:

FIG. 1A is a schematic block diagram illustrating one embodiment of asystem for dynamically determining boundary word line voltage shift;

FIG. 1B is a schematic block diagram illustrating another embodiment ofa system for dynamically determining boundary word line voltage shift;

FIG. 2 is a schematic block diagram illustrating one embodiment of astring of storage cells;

FIG. 3A is a schematic block diagram illustrating one embodiment of anarray of storage cells;

FIG. 3B is a diagram of the voltage shift across an array of storagecells;

FIG. 4 is a schematic block diagram illustrating one embodiment of athree-dimensional (3D), vertical NAND flash memory structure;

FIG. 5 is a schematic block diagram illustrating one embodiment of avoltage determination component for dynamically determining boundaryword line voltage shift;

FIG. 6 is a schematic block diagram illustrating one embodiment ofanother voltage determination component for dynamically determiningboundary word line voltage shift;

FIG. 7 is a schematic flow chart diagram illustrating one embodiment ofa method for dynamically determining boundary word line voltage shift;and

FIG. 8 is a schematic flow chart diagram illustrating one embodiment ofanother method for dynamically determining boundary word line voltageshift.

DETAILED DESCRIPTION

Aspects of the present disclosure may be embodied as an apparatus,system, method, or computer program product. Accordingly, aspects of thepresent disclosure may take the form of an entirely software embodiment(including firmware, resident software, micro-code, or the like) or anembodiment combining software and hardware aspects that may allgenerally be referred to herein as a “circuit,” “module,” “apparatus,”or “system.” Furthermore, aspects of the present disclosure may take theform of a computer program product embodiment on one or morenon-transitory computer-readable storage media storing computer-readableand/or executable program code.

Many of the functional units described in this specification have beenlabeled as modules, in order to more particularly emphasize theirimplementation independence. For example, a module may be implemented asa hardware circuit comprising custom VLSI circuits or gate arrays,off-the-shelf semiconductors such as logic chips, transistors, or otherdiscrete components. A module may also be implemented in programmablehardware devices such as field programmable gate arrays, programmablearray logic, programmable logic devices, or the like.

Modules may also be implemented at least partially in software forexecution by various types of processors. An identified module ofexecutable code may, for instance, comprise one or more physical orlogical blocks of computer instructions that may, for instance, beorganized as an object, procedure, or function. Nevertheless, theexecutables of an identified module need not be physically locatedtogether, but may comprise disparate instructions stored in differentlocations that, when joined logically together, comprise the module andachieve the stated purpose for the module.

Indeed, a module of executable code may include a single instruction, ormany instructions, and may even be distributed over several differentcode segments, among different programs, across several memory devices,or the like. Where a module or portions of a module are implemented insoftware, the software portions may be stored on one or morecomputer-readable and/or executable storage media. Any combination ofone or more computer-readable storage media may be utilized. Acomputer-readable storage medium may include, for example, but notlimited to, an electronic, magnetic, optical, electromagnetic, infrared,or semiconductor system, apparatus, or device, or any suitablecombination of the foregoing, but would not include propagating signals.In the context of this document, a computer-readable and/or executablestorage medium may be any tangible and/or non-transitory medium that maycontain or store a program for use by or in connection with aninstruction execution system, apparatus, processor, or device.

Computer program code for carrying out operations for aspects of thepresent disclosure may be written in any combination of one or moreprogramming languages, including an object oriented programming languagesuch as Python, Java, Smalltalk, C++, C#, Objective C, or the like,conventional procedural programming languages, such as the “C”programming language, scripting programming languages, and/or othersimilar programming languages. The program code may execute partly orentirely on one or more of a user's computer and/or on a remote computeror server over a data network or the like.

A component, as used herein, comprises a tangible, physical,non-transitory device. For example, a component may be implemented as ahardware logic circuit comprising custom VLSI circuits, gate arrays, orother integrated circuits; off-the-shelf semiconductors such as logicchips, transistors, or other discrete devices; and/or other mechanicalor electrical devices. A component may also be implemented inprogrammable hardware devices such as field programmable gate arrays,programmable array logic, programmable logic devices, or the like. Acomponent may comprise one or more silicon integrated circuit devices(e.g., chips, die, die planes, packages) or other discrete electricaldevices, in electrical communication with one or more other componentsthrough electrical lines of a printed circuit board (PCB) or the like.Each of the modules described herein, in certain embodiments, mayalternatively be embodied by or implemented as a component.

A circuit, as used herein, comprises a set of one or more electricaland/or electronic components providing one or more pathways forelectrical current. In certain embodiments, a circuit may include areturn pathway for electrical current, so that the circuit is a closedloop. In another embodiment, however, a set of components that does notinclude a return pathway for electrical current may be referred to as acircuit (e.g., an open loop). For example, an integrated circuit may bereferred to as a circuit regardless of whether the integrated circuit iscoupled to ground (as a return pathway for electrical current) or not.In various embodiments, a circuit may include a portion of an integratedcircuit, an integrated circuit, a set of integrated circuits, a set ofnon-integrated electrical and/or electrical components with or withoutintegrated circuit devices, or the like. In one embodiment, a circuitmay include custom VLSI circuits, gate arrays, logic circuits, or otherintegrated circuits; off-the-shelf semiconductors such as logic chips,transistors, or other discrete devices; and/or other mechanical orelectrical devices. A circuit may also be implemented as a synthesizedcircuit in a programmable hardware device such as field programmablegate array, programmable array logic, programmable logic device, or thelike (e.g., as firmware, a netlist, or the like). A circuit may compriseone or more silicon integrated circuit devices (e.g., chips, die, dieplanes, packages) or other discrete electrical devices, in electricalcommunication with one or more other components through electrical linesof a printed circuit board (PCB) or the like. Each of the modulesdescribed herein, in certain embodiments, may be embodied by orimplemented as a circuit.

Reference throughout this specification to “one embodiment,” “anembodiment,” or similar language means that a particular feature,structure, or characteristic described in connection with the embodimentis included in at least one embodiment of the present disclosure. Thus,appearances of the phrases “in one embodiment,” “in an embodiment,” andsimilar language throughout this specification may, but do notnecessarily, all refer to the same embodiment, but mean “one or more butnot all embodiments” unless expressly specified otherwise. The terms“including,” “comprising,” “having,” and variations thereof mean“including but not limited to” unless expressly specified otherwise. Anenumerated listing of items does not imply that any or all of the itemsare mutually exclusive and/or mutually inclusive, unless expresslyspecified otherwise. The terms “a,” “an,” and “the” also refer to “oneor more” unless expressly specified otherwise.

In addition, as used herein, the term “set” can mean “one or more,”unless expressly specified otherwise. The term “sets” can mean multiplesof or a plurality of “one or mores,” “ones or more,” and/or “ones ormores” consistent with set theory, unless expressly specified otherwise.

Aspects of the present disclosure are described below with reference toschematic flowchart diagrams and/or schematic block diagrams of methods,apparatuses, systems, and computer program products according toembodiments of the disclosure. It will be understood that each block ofthe schematic flowchart diagrams and/or schematic block diagrams, andcombinations of blocks in the schematic flowchart diagrams and/orschematic block diagrams, can be implemented by computer programinstructions. These computer program instructions may be provided to aprocessor of a computer or other programmable data processing apparatusto produce a machine, such that the instructions, which execute via theprocessor or other programmable data processing apparatus, create meansfor implementing the functions and/or acts specified in the schematicflowchart diagrams and/or schematic block diagrams block or blocks.

It should also be noted that, in some alternative implementations, thefunctions noted in the block may occur out of the order noted in thefigures. For example, two blocks shown in succession may, in fact, beexecuted substantially concurrently, or the blocks may sometimes beexecuted in the reverse order, depending upon the functionalityinvolved. Other steps and methods may be conceived that are equivalentin function, logic, or effect to one or more blocks, or portionsthereof, of the illustrated figures. Although various arrow types andline types may be employed in the flowchart and/or block diagrams, theyare understood not to limit the scope of the corresponding embodiments.For instance, an arrow may indicate a waiting or monitoring period ofunspecified duration between enumerated steps of the depictedembodiment.

In the following detailed description, reference is made to theaccompanying drawings, which form a part thereof. The foregoing summaryis illustrative only and is not intended to be in any way limiting. Inaddition to the illustrative aspects, embodiments, and featuresdescribed above, further aspects, embodiments, and features will becomeapparent by reference to the drawings and the following detaileddescription. The description of elements in each figure may refer toelements of proceeding figures. Like numbers may refer to like elementsin the figures, including alternate embodiments of like elements.

FIG. 1A is a block diagram of one embodiment of a system 100 including avoltage determination component 150 for a controller 126 of anon-volatile memory device 120. The voltage determination component 150may be part of and/or in communication with a controller 126, anon-volatile memory element 123, a device driver, or the like. Thevoltage determination component 150 may operate on a non-volatile memorysystem 102 of a computing device 110, which may comprise a processor111, volatile memory 112, and a communication interface 113. Theprocessor 111 may comprise one or more central processing units, one ormore general-purpose processors, one or more application-specificprocessors, one or more virtual processors (e.g., the computing device110 may be a virtual machine operating within a host), one or moreprocessor cores, or the like. The communication interface 113 maycomprise one or more network interfaces configured to communicativelycouple the computing device 110 and/or controller 126 to a communicationnetwork 115, such as an Internet Protocol (IP) network, a Storage AreaNetwork (SAN), wireless network, wired network, or the like.

The non-volatile memory device 120, in various embodiments, may bedisposed in one or more different locations relative to the computingdevice 110. In one embodiment, the non-volatile memory device 120comprises one or more non-volatile memory elements 123, such assemiconductor chips or packages or other integrated circuit devicesdisposed on one or more printed circuit boards, storage housings, and/orother mechanical and/or electrical support structures. For example, thenon-volatile memory device 120 may comprise one or more direct inlinememory module (DIMM) cards, one or more expansion cards and/or daughtercards, a solid-state-drive (SSD) or other hard drive device, and/or mayhave another memory and/or storage form factor. The non-volatile memorydevice 120 may be integrated with and/or mounted on a motherboard of thecomputing device 110, installed in a port and/or slot of the computingdevice 110, installed on a different computing device 110 and/or adedicated storage appliance on the network 115, in communication withthe computing device 110 over an external bus (e.g., an external harddrive), or the like.

The non-volatile memory device 120, in one embodiment, may be disposedon a memory bus of a processor 111 (e.g., on the same memory bus as thevolatile memory 112, on a different memory bus from the volatile memory112, in place of the volatile memory 112, or the like). In a furtherembodiment, the non-volatile memory device 120 may be disposed on aperipheral bus of the computing device 110, such as a peripheralcomponent interconnect express (PCI Express or PCIe) bus, a serialAdvanced Technology Attachment (SATA) bus, a parallel AdvancedTechnology Attachment (PATA) bus, a small computer system interface(SCSI) bus, a FireWire bus, a Fibre Channel connection, a UniversalSerial Bus (USB), a PCIe Advanced Switching (PCIe-AS) bus, or the like.In another embodiment, the non-volatile memory device 120 may bedisposed on a data network 115, such as an Ethernet network, anInfiniband network, SCSI RDMA over a network 115, a storage area network(SAN), a local area network (LAN), a wide area network (WAN) such as theInternet, another wired and/or wireless network 115, or the like.

The computing device 110 may further comprise a non-transitory,computer-readable storage medium 114. The computer-readable storagemedium 114 may comprise executable instructions configured to cause thecomputing device 110 (e.g., processor 111) to perform steps of one ormore of the methods disclosed herein. Alternatively, or in addition, thevoltage determination component 150 may be embodied as one or morecomputer-readable instructions stored on the non-transitory storagemedium 114.

The non-volatile memory system 102, in the depicted embodiment, includesa voltage determination component 150. The voltage determinationcomponent 150, in one embodiment, is configured to determine a readvoltage threshold and/or a read voltage threshold shift for a boundaryword line. In certain embodiments, the voltage determination component150 detects a trigger condition associated with a boundary word line ofa partially programmed erase block of an array of non-volatile memorycells. In further embodiments, the voltage determination component 150determines a read voltage threshold for the boundary word line anddynamically calculates a read voltage threshold shift for the boundaryword line based on the determined read voltage threshold for theboundary word line and a baseline read voltage threshold.

In one embodiment, the voltage determination component 150 may compriselogic hardware of one or more non-volatile memory devices 120, such as acontroller 126, a non-volatile memory element 123, a device controller,a field-programmable gate array (FPGA) or other programmable logic,firmware for an FPGA or other programmable logic, microcode forexecution on a microcontroller, an application-specific integratedcircuit (ASIC), or the like. In another embodiment, the voltagedetermination component 150 may comprise executable software code, suchas a device driver or the like, stored on the computer-readable storagemedium 114 for execution on the processor 111. In a further embodiment,the voltage determination component 150 may include a combination ofboth executable software code and logic hardware.

In one embodiment, the voltage determination component 150 is configuredto receive I/O requests from a device driver or other executableapplication via a bus 125 or the like. The voltage determinationcomponent 150 may be further configured to transfer data to/from adevice driver and/or storage clients 116 via the bus 125. Accordingly,the voltage determination component 150, in some embodiments, maycomprise and/or be in communication with one or more direct memoryaccess (DMA) modules, remote DMA modules, bus controllers, bridges,buffers, and so on to facilitate the transfer of memory/storage requestsand storage operations of associated program data. In anotherembodiment, the voltage determination component 150 may receive storagerequests as an API call from a storage client 116, as an IO-CTL command,or the like.

According to various embodiments, a controller 126 in communication withone or more voltage determination components 150 may manage one or morenon-volatile memory devices 120 and/or non-volatile memory elements 123.The non-volatile memory device(s) 120 may comprise recording, memory,and/or storage devices, such as solid-state storage device(s) and/orsemiconductor storage device(s) that are arranged and/or partitionedinto a plurality of addressable media storage locations. As used herein,a media storage location refers to any physical unit of memory (e.g.,any quantity of physical storage media on a non-volatile memory device120). Memory units may include, but are not limited to: pages, memorydivisions, blocks, sectors, collections or sets of physical storagelocations (e.g., logical pages, logical blocks), or the like.

A device driver and/or the controller 126, in certain embodiments, maypresent a logical address space 134 to the storage clients 116. As usedherein, a logical address space 134 refers to a logical representationof memory resources. The logical address space 134 may comprise aplurality (e.g., range) of logical addresses. As used herein, a logicaladdress refers to any identifier for referencing a memory resource(e.g., data), including, but not limited to: a logical block address(LBA), cylinder/head/sector (CHS) address, a file name, an objectidentifier, an inode, a Universally Unique Identifier (UUID), a GloballyUnique Identifier (GUID), a hash code, a signature, an index entry, arange, an extent, or the like.

A device driver for the non-volatile memory device 120 may maintainmetadata 135, such as a logical to physical address mapping structure,to map logical addresses of the logical address space 134 to mediastorage locations on the non-volatile memory device(s) 120. A devicedriver may be configured to provide storage services to one or morestorage clients 116. The storage clients 116 may include local storageclients 116 operating on the computing device 110 and/or remote, storageclients 116 accessible via the network 115 and/or network interface 113.The storage clients 116 may include, but are not limited to: operatingsystems, file systems, database applications, server applications,kernel-level processes, user-level processes, applications, and thelike.

A device driver may be communicatively coupled to one or morenon-volatile memory devices 120. The one or more non-volatile memorydevices 120 may include different types of non-volatile memory devicesincluding, but not limited to: solid-state storage devices,semiconductor storage devices, SAN storage resources, or the like. Theone or more non-volatile memory devices 120 may comprise one or morerespective controllers 126 and non-volatile memory media 122. A devicedriver may provide access to the one or more non-volatile memory devices120 via a traditional block I/O interface 131. Additionally, a devicedriver may provide access to enhanced functionality through the SCMinterface 132. The metadata 135 may be used to manage and/or track dataoperations performed through any of the Block I/O interface 131, SCMinterface 132, cache interface 133, or other, related interfaces.

The cache interface 133 may expose cache-specific features accessiblevia a device driver for the non-volatile memory device 120. Also, insome embodiments, the SCM interface 132 presented to the storage clients116 provides access to data transformations implemented by the one ormore non-volatile memory devices 120 and/or the one or more controllers126.

A device driver may present a logical address space 134 to the storageclients 116 through one or more interfaces. As discussed above, thelogical address space 134 may comprise a plurality of logical addresses,each corresponding to respective media locations of the one or morenon-volatile memory devices 120. A device driver may maintain metadata135 comprising any-to-any mappings between logical addresses and medialocations, or the like.

A device driver may further comprise and/or be in communication with anon-volatile memory device interface 139 configured to transfer data,commands, and/or queries to the one or more non-volatile memory devices120 over a bus 125, which may include, but is not limited to: a memorybus of a processor 111, a peripheral component interconnect express (PCIExpress or PCIe) bus, a serial Advanced Technology Attachment (ATA) bus,a parallel ATA bus, a small computer system interface (SCSI), FireWire,Fibre Channel, a Universal Serial Bus (USB), a PCIe Advanced Switching(PCIe-AS) bus, a network 115, Infiniband, SCSI RDMA, or the like. Thenon-volatile memory device interface 139 may communicate with the one ormore non-volatile memory devices 120 using input-output control (IO-CTL)command(s), IO-CTL command extension(s), remote direct memory access, orthe like.

The communication interface 113 may comprise one or more networkinterfaces configured to communicatively couple the computing device 110and/or the controller 126 to a network 115 and/or to one or more remote,network-accessible storage clients 116. The storage clients 116 mayinclude local storage clients 116 operating on the computing device 110and/or remote, storage clients 116 accessible via the network 115 and/orthe network interface 113. The controller 126 is part of and/or incommunication with one or more non-volatile memory devices 120. AlthoughFIG. 1A depicts a single non-volatile memory device 120, the disclosureis not limited in this regard and could be adapted to incorporate anynumber of non-volatile memory devices 120.

The non-volatile memory device 120 may comprise one or more memoryelements 123 of non-volatile memory media 122, which may include, but isnot limited to: random access memory (RAM), resistive RAM (ReRAM),Memristor memory, programmable metallization cell memory, phase-changememory (PCM, PCME, PRAM, PCRAM, ovonic unified memory, chalcogenide RAM,or C-RAM), NAND flash memory (e.g., 2D NAND flash memory, 3D NAND flashmemory), NOR flash memory, nano random access memory (nano RAM or NRAM),nanocrystal wire-based memory, silicon-oxide based sub-10 nanometerprocess memory, graphene memory, Silicon-Oxide-Nitride-Oxide-Silicon(SONOS), programmable metallization cell (PMC), conductive-bridging RAM(CBRAM), magneto-resistive RAM (MRAM), magnetic storage media (e.g.,hard disk, tape, etc.), optical storage media, and/or the like, amongother devices that are possible and contemplated herein. The one or morememory elements 123 of non-volatile memory media 122, in certainembodiments, comprise storage class memory (SCM).

While legacy technologies, such as NAND flash, may be block and/or pageaddressable, storage class memory, in one embodiment, is byteaddressable. In further embodiments, SCM may be faster and/or have alonger life (e.g., endurance) than NAND flash; may have a lower cost,use less power, and/or have a higher storage density than DRAM; or offerone or more other benefits or improvements when compared to othertechnologies. For example, storage class memory may comprise one or morenon-volatile memory elements 123 of ReRAM, Memristor memory,programmable metallization cell memory, phase-change memory, nano RAM,nanocrystal wire-based memory, silicon-oxide based sub-10 nanometerprocess memory, graphene memory, SONOS memory, PMC memory, CBRAM, MRAM,and/or variations thereof.

While the non-volatile memory media 122 is referred to herein as “memorymedia,” in various embodiments, the non-volatile memory media 122 maymore generally comprise one or more non-volatile recording media capableof recording data, which may be referred to as a non-volatile memorymedium, a non-volatile storage medium, and/or the like. Further, thenon-volatile memory device 120, in various embodiments, may comprise anon-volatile recording device, a non-volatile memory device, anon-volatile storage device, and/or the like.

The non-volatile memory media 122 may comprise one or more non-volatilememory elements 123, which may include, but are not limited to: chips,packages, planes, die, and/or the like. A controller 126 may beconfigured to manage data operations on the non-volatile memory media122, and may comprise one or more processors, programmable processors(e.g., FPGAs), ASICs, micro-controllers, or the like. In someembodiments, the controller 126 is configured to store data on and/orread data from the non-volatile memory media 122, to transfer datato/from the non-volatile memory device 120, and so on.

The controller 126 may be communicatively coupled to the non-volatilememory media 122 by way of a bus 127. The bus 127 may comprise an I/Obus for communicating data to/from the non-volatile memory elements 123.The bus 127 may further comprise a control bus for communicatingaddressing and other command and control information to the non-volatilememory elements 123. In some embodiments, the bus 127 maycommunicatively couple the non-volatile memory elements 123 to thecontroller 126 in parallel. This parallel access may allow thenon-volatile memory elements 123 to be managed as a group, forming alogical memory element 129. The logical memory element may bepartitioned into respective logical memory units (e.g., logical pages)and/or logical memory divisions (e.g., logical blocks). The logicalmemory units may be formed by logically combining physical memory unitsof each of the non-volatile memory elements.

The controller 126 may organize a block of word lines within anon-volatile memory element 123, in certain embodiments, using addressesof the word lines, such that the word lines are logically organized intoa monotonically increasing sequence (e.g., decoding and/or translatingaddresses for word lines into a monotonically increasing sequence, orthe like). In a further embodiment, word lines of a block within anon-volatile memory element 123 may be physically arranged in amonotonically increasing sequence of word line addresses, withconsecutively addressed word lines also being physically adjacent (e.g.,WL0, WL1, WL2, . . . WLN).

The controller 126 may comprise and/or be in communication with a devicedriver executing on the computing device 110. A device driver mayprovide storage services to the storage clients 116 via one or moreinterfaces 131, 132, and/or 133. In some embodiments, a device driverprovides a block-device I/O interface 131 through which storage clients116 perform block-level I/O operations. Alternatively, or in addition, adevice driver may provide a storage class memory (SCM) interface 132,which may provide other storage services to the storage clients 116. Insome embodiments, the SCM interface 132 may comprise extensions to theblock device interface 131 (e.g., storage clients 116 may access the SCMinterface 132 through extensions or additions to the block deviceinterface 131). Alternatively, or in addition, the SCM interface 132 maybe provided as a separate API, service, and/or library.

A device driver may be further configured to provide a cache interface133 for caching data using the non-volatile memory system 102. A devicedriver may further comprise a non-volatile memory device interface 139that is configured to transfer data, commands, and/or queries to thecontroller 126 over a bus 125, as described above.

FIG. 1B illustrates an embodiment of a non-volatile storage device 210that may include one or more memory die and/or chips 212. Memory die212, in some embodiments, includes an array (e.g., two-dimensional (2D),three dimensional (3D), etc.) of memory cells, die controller 220, andread/write circuits 230A/230B. In one embodiment, access to the memoryarray 200 by various peripheral circuits is implemented in a symmetricfashion, on opposite sides of the array, so that the densities of accesslines and circuitry on each side are reduced by half. The read/writecircuits 230A/230B, in a further embodiment, can include multiple senseblocks 250 that allow a page of memory cells to be read and/orprogrammed in parallel.

The memory array 200, in various embodiments, is addressable using wordlines via row decoders 240A/240B and using bit lines via column decoders242A/242B. In some embodiments, a controller 244 is included in the samememory device 210 (e.g., a removable storage card or package) as the oneor more memory die 212. Commands and data are transferred between thehost and controller 244 via lines 232 and between the controller and theone or more memory die 212 via lines 234. One implementation can includemultiple chips 212.

Die controller 220, in one embodiment, cooperates with the read/writecircuits 230A/230B to perform memory operations on the memory array 200.The die controller 220, in certain embodiments, includes a voltagedetermination component 150, a state machine 222, and an on-chip addressdecoder 224. In one embodiment, the state machine 222 comprises at leasta portion of the voltage determination component 150. In a furtherembodiment, the controller 244 comprises at least a portion of thevoltage determination component 150. In various embodiments, one or moreof the sense blocks 250 comprises at least a portion of the voltagedetermination component 150. The voltage determination component(s) 150discussed with reference to FIG. 1B may be similar to the voltagedetermination component(s) 150 discussed with reference to FIG. 1A.

The state machine 222, in one embodiment, provides chip-level control ofmemory operations. The on-chip address decoder 224 provides an addressinterface to convert between the address that is used by the host or amemory controller to the hardware address used by the decoders 240A,240B, 242A, and 242B. In certain embodiments, the state machine 222includes an embodiment of the voltage determination component 150. Thevoltage determination component 150, in certain embodiments, is embodiedas software in a device driver, hardware in a controller 244, and/orhardware in a die controller 220 and/or state machine 222. In oneembodiment, one or any combination of die controller 220, voltagedetermination component 150, decoder circuit 224, state machine circuit222, decoder circuit 242A, decoder circuit 242B, decoder circuit 240A,decoder circuit 240B, read/write circuits 230A, read/write circuits230B, and/or controller 244 can be referred to as one or more managingcircuits.

FIG. 2 depicts one embodiment of a NAND string comprising a plurality ofstorage elements. The NAND string depicted in FIG. 2, in someembodiments, includes four transistors 260, 262, 264, and 266 connectedin series and located between a first select transistor 270 and a secondselect transistor 272. In some embodiments, a transistor 260, 262, 264,266 includes a control gate and a floating gate. A control gate 290,292, 294, 296, in one embodiment, is connected to, or comprises aportion of, a word line. In a further embodiment, a transistor 260, 262,264, 266 is a storage element, storage cell, or the like, also referredto as a memory cell 200. In some embodiments, a storage element mayinclude multiple transistors 260, 262, 264, 266.

The first select transistor 270, in some embodiments, gates/connects theNAND string connection to a bit line 280 via a drain select gate SGD.The second select transistor 272, in certain embodiments, gates/connectsthe NAND string connection to a source line 282 via a source select gateSGS. The first select transistor 270, in a further embodiment, iscontrolled by applying a voltage to a corresponding select gate 286. Thesecond select transistor 272, in some embodiments, is controlled byapplying a voltage to corresponding select gate 288.

As shown in FIG. 2, the source line 282, in one embodiment, is connectedto the sources of each transistor/storage cell 260, 262, 264, and 266 inthe NAND string. The NAND string, in some embodiments, may include somestorage elements 260, 262, 264, and 266 that have been programmed andsome storage elements 260, 262, 264, and 266 that have not beenprogrammed. As described in more detail below, the voltage determinationcomponent 150 controls whether portions of a storage device, such as aNAND string, are used for memory and/or storage operations.

FIG. 3A is a circuit diagram depicting a plurality of NAND strings 320,340, 360, 380 (collectively 301). The architecture for a flash memorysystem using a NAND structure may include several NAND strings 301. Forexample, FIG. 3A illustrates NAND strings 301 in a memory array 200 thatincludes multiple NAND strings 301. In the depicted embodiment, eachNAND string 320, 340, 360, 380 includes drain select transistors 322,342, 362, 382, source select transistors 327, 347, 367, 387, and storageelements 323-326, 343-346, 363-366, 383-386. While four storage elements323-326, 343-346, 363-366, 383-386 per NAND string 301 are illustratedfor simplicity, some NAND strings 301 can include any number of storageelements (e.g., thirty-two, sixty-four, or the like storage elements,among other storage elements that are possible and contemplated herein).

NAND strings 301, in one embodiment, are connected to a source line 319by source select transistors 327, 347, 367, 387. A selection line SGSmay be used to control the source side select transistors. The variousNAND strings 301, in one embodiment, are connected to bit lines 321,341, 361, 381 by drain select transistors 322, 342, 362, 382. The drainselect transistors 322, 342, 362, 382 may be controlled by a drainselect line SGD. In some embodiments, the select lines do notnecessarily need to be in common among the NAND strings 301; that is,different select lines can be provided for different NAND strings 301.

As described above, each word line WL0-WLn (collectively 303) comprisesone or more storage elements 323-383, 324-384, 325-385, 326-386. In thedepicted embodiment, each bit line 321, 341, 361, 381 and the respectiveNAND string 320, 340, 360, 380 comprise the columns of the memory array200, storage block, erase block, or the like. The word lines 303, insome embodiments, comprise the rows of the memory array 200, storageblock, erase block, or the like. Each word line 303, in someembodiments, connects the control gates of each storage element 323-383,324-384, 325-385, 326-386 in a row. Alternatively, the control gates maybe provided by the word lines 303 themselves. In some embodiments, aword line 303 may include tens, hundreds, thousands, millions, or thelike of storage elements 323-383, 324-384, 325-385, 326-386.

In one embodiment, the last programmed word line 303 of a NAND string301 of a partially programmed erase block is known as a boundary wordline. For example, the array of storage cells 323-326, 343-346, 363-366illustrated in FIG. 3A may be an erase block, and the erase block maynot be fully programmed, meaning not every storage cell 323-326,343-346, 363-366 in the erase block currently stores data, e.g., somestorage cells 326, 346, 365-366, 385-386 along WL1 and WL0 are notprogrammed. In such an embodiment, the programmed storage cells 325,345, 364, 384 that are adjacent to the unprogrammed storage cells 326,346, 365, 385 are the storage cells comprising the last programmed wordline, otherwise known herein as boundary word line storage cells 302,which may apply to both two-dimensional and three-dimensional NANDstrings. The boundary word line storage cells 302 may have differentstorage/voltage characteristics than the other programmed storage cellsin the erase block due to various factors such as program disturb, readdisturb, temperature, retention times, read counts, and/or the like.Furthermore, the storage/voltage characteristics for boundary word linestorage cells 302 may vary across different storage dies 212, eraseblocks, word lines, and/or the like.

In conventional storage systems, a fixed read voltage shift may be usedto compensate for voltage drifts of the boundary word line storage cells302 and the other programmed storage cells caused by the above mentionedfactors; however, using the same fixed read voltage shift for theboundary word line storage cells 302 as the other programmed storagecells may not be optimal for the boundary word line storage cells 302because of their different storage/voltage characteristics due to theirlocation in the erase block, e.g., their location adjacent to anunprogrammed storage cell. For instance, because the boundary word linestorage cells 302 are adjacent to a single programmed storage cell,their read voltage threshold may not have drifted as much due to readand/or program disturbs as compared to other programmed storage cellsthat are adjacent to two programmed storage cells. Furthermore, theboundary word line storage cells 302 may react differently to dataretention conditions, temperature conditions, and/or the like due totheir locations on the erase block. Accordingly, static or fixed readvoltage shifts may not be the best approach to compensate for readvoltage threshold drifts of boundary word line storage cells 302.

In one embodiment, each storage element 323-326, 343-346, 363-366,383-386 is configured to store data. For example, when storing one bitof digital data, the range of possible threshold voltages (“VTH”) ofeach storage element 323-326, 343-346, 363-366, 383-386 may be dividedinto two ranges that are assigned logical data “1” and “0.” In oneexample of a NAND type flash memory, the VTH may be negative after thestorage elements 323-326, 343-346, 363-366, 383-386 are erased, anddefined as logic “1.” In one embodiment, the VTH after a programoperation is positive and defined as logic “0.”

When the VTH is negative and a read is attempted, in some embodiments,storage elements 323-326, 343-346, 363-366, 383-386 will turn on toindicate logic “1” is being stored. When the VTH is positive and a readoperation is attempted, in a further embodiment, a storage element willnot turn on, which indicates that logic “0” is stored. Each storageelement 323-383, 324-384, 325-385, 326-386 may also store multiplelevels of information, for example, multiple bits of digital data. Insuch an embodiment, the range of VTH value is divided into the number oflevels of data. For example, if four levels of information can be storedin each storage element 323-326, 343-346, 363-366, 383-386, there willbe four VTH ranges assigned to the data values “11”, “10”, “01”, and“00.”

In one example of a NAND type memory, the VTH after an erase operationmay be negative and defined as “11.” Positive VTH values may be used forthe states of “10”, “01”, and “00.” In one embodiment, the specificrelationship between the data programmed into the storage elements323-326, 343-346, 363-366, 383-386 and the threshold voltage ranges ofthe storage elements 323-326, 343-346, 363-366, 383-386 depends upon thedata encoding scheme adopted for the storage elements 323-326, 343-346,363-366, 383-386.

In some embodiments, portions of the storage elements 323-326, 343-346,363-366, 383-386 may be defective. In such an embodiment, the voltagedetermination component 150 may manage which portions of the storageelements 323-326, 343-346, 363-366, and 383-386 are used for operations.

FIG. 3B illustrates the read voltage threshold distribution and shiftdifferences across an array of storage cells between boundary word linestorage cells 302 and non-boundary word line storage cells (e.g.,programmed storage cells that are not the last programmed storage cellsof a word line). For instance, as illustrated in FIG. 3B, the readvoltage threshold shift distributions 390 of the boundary word linestorage cells 302 are shifted even further than the read voltagethreshold shift distributions 392 of non-boundary word line storagecells. Furthermore, in certain embodiments, lower voltage states 394,e.g., voltage states towards the left of the graph depicted in FIG. 3B,for boundary word line storage cells 302 tend to have larger readvoltage threshold shifts than lower voltage states 396 for non-boundaryword line storage cells. Due to the differences in read voltagethreshold shifts between boundary word line storage cells 302 andnon-boundary word line storage cells, a static or fixed read voltageshift table may not be sufficient to correct or compensate for the readvoltage threshold shifts of the boundary word line storage cells 302.However, as described in more detail below, the voltage determinationcomponent 150 dynamically determines the read voltage threshold shift ofthe boundary word line storage cells 302 to compensate for the readvoltage shift differences.

FIG. 4 illustrates one embodiment of a cross-sectional view of a 3D,vertical NAND flash memory structure 429 or string 429. In oneembodiment, the vertical column 432 is round and includes four layers;however, in other embodiments more or less than four layers can beincluded and other shapes can be used (e.g., a “U” shape instead of an“I” shape or the like). In one embodiment, a vertical column 432includes an inner core layer 470 that is made of a dielectric, such asSiO2. Other materials can also be used. Surrounding inner core 470 ispolysilicon channel 471. Materials other than polysilicon can also beused. Note that it is the channel 471 that connects to the bit line.Surrounding channel 471 is a tunneling dielectric 472. In oneembodiment, tunneling dielectric 472 has an ONO structure. Surroundingtunneling dielectric 472 is a shared charge-trapping layer 473, such as(for example) Silicon Nitride. Other materials and/or structures canalso be used. That is, the technology discussed herein is not limited toany particular material and/or structure.

As shown, FIG. 4 depicts dielectric layers DLL49, DLL50, DLL51, DLL52and DLL53, as well as word line layers WLL43, WLL44, WLL45, WLL46, andWLL47. Each of the word line layers includes a word line region 476surrounded by an aluminum oxide layer 477, which is surrounded by ablocking oxide (SiO2) layer 478. The physical interaction of the wordline layers with the vertical column forms the memory cells. Thus, amemory cell, in one embodiment, comprises channel 471, tunnelingdielectric 472, charge-trapping layer 473 (e.g., shared with othermemory cells), blocking oxide layer 478, aluminum oxide layer 477 andword line region 476. In some embodiments, the blocking oxide layer 478and aluminum oxide layer 477, may be replaced by a single layer ofmaterial with insulating properties or by more than 2 layers ofdifferent material with insulating properties. Furthermore, thematerials used are not limited to silicon dioxide (SiO2) or aluminumoxide. For example, word line layer WLL47 and a portion of verticalcolumn 432 comprise a memory cell MC1. Word line layer WLL46 and aportion of vertical column 432 comprise a memory cell MC2. Word linelayer WLL45 and a portion of vertical column 432 comprise a memory cellMC3. Word line layer WLL44 and a portion of vertical column 432 comprisea memory cell MC4. Word line layer WLL43 and a portion of verticalcolumn 432 comprise a memory cell MC5. In other architectures, a memorycell may have a different structure; however, the memory cell wouldstill be the storage unit.

When a memory cell is programmed, electrons are stored in a portion ofthe charge-trapping layer 473 that is associated with the memory cell.These electrons are drawn into the charge-trapping layer 473 from thechannel 471, through the tunneling dielectric 472, in response to anappropriate voltage on word line region 476. The threshold voltage (Vth)of a memory cell is increased in proportion to the amount of storedcharge. In one embodiment, the programming is achieved throughFowler-Nordheim tunneling of the electrons into the charge-trappinglayer. During an erase operation, the electrons return to the channel orholes are injected into the charge-trapping layer to recombine withelectrons. In one embodiment, erasing is achieved using hole injectioninto the charge-trapping layer via a physical mechanism such as gateinduced drain leakage (GIDL).

Storage cells in the same location or position in different memorystructures 429 (e.g., different NAND strings 429) on different bitlines, in certain embodiments, may be on the same word line. Each wordline may store one page of data, such as when 1-bit of data is storedper cell (SLC); two pages of data, such as when 2-bits of data arestored per cell (MLC); three pages of data, such as when 3-bits of dataare stored per cell (TLC); four pages of data, such as when 4-bits ofdata are stored per cell (QLC); or another number of pages of data.

In the depicted embodiment, a vertical, 3D NAND flash memory structure429 comprises an “I” shaped memory structure 429. In other embodiments,a vertical, 3D NAND flash memory structure 429 may comprise a “U” shapedstructure, or may have another vertical and/or stacked architecture. Incertain embodiments, four sets of strings 429 (e.g., four sets of 48word lines, or another predefined number of word lines) may form anerase block, while in other embodiments, fewer or more than four sets ofstrings 429 may form an erase block. As may be appreciated, any suitablenumber of storage cells may be part of a single string 429. In oneembodiment, a single string 429 includes 48 storage cells.

FIG. 5 is a schematic block diagram illustrating one embodiment of avoltage determination component 150 for dynamically determining boundaryword line voltage shift. The voltage determination component 150, in oneembodiment, includes one or more of a trigger detection component 502, avoltage component 504, and a voltage shift component 506, which aredescribed in more detail below.

In one embodiment, the trigger detection component 502 is configured todetect a trigger condition associated with a boundary word line storagecell 302 of a partially programmed erase block of an array 200 ofnon-volatile memory cells. As used herein, a boundary word line storagecell 302 is a last programmed word line 303 of a NAND string 301, asdescribed above with reference to FIG. 3A. The boundary word linestorage cell 302, for example, may be the last programmed word line 303of a NAND string 301 of a partially programmed erase block such that thestorage cells of a boundary word line 302 are adjacent to a programmedmemory cell and an unprogrammed memory cell of the respective NANDstrings 301.

The trigger detection component 502 is configured to detect, monitor,check for, sense, and/or the like one or more trigger conditionsassociated with a boundary word line storage cell 302. As explainedbelow, the detection of the trigger condition may initiate, cause,trigger, start, and/or the like recalibration of a read voltagethreshold shift of a boundary word line storage cell 302, which, asexplained above, may have different voltage threshold characteristics,e.g., voltage shift from a baseline voltage, than other programmedstorage cells of an erase block.

In one embodiment, the trigger condition includes detecting that apredetermined amount of time has passed since the read voltage thresholdshift for the boundary word line storage cell 302 was previouslydetermined, since the last read operation performed on the boundary wordline storage cell 302, since a program operation performed on theboundary word line storage cell 302, and/or the like. For example, aftera boundary word line storage cell 302 is programmed, the voltagedetermination component 150, a controller 126, and/or the like may starta timer that is set for a predefined period of time, such as two hours.When the timer expires, the voltage determination component 150 and/orthe controller 126 may send a notification, a signal, and/or anotherindication to the trigger detection component 502 to indicate that thetimer has expired.

In one embodiment, the trigger condition includes determining that anerror rate for a boundary word line storage cell 302 satisfies apredetermined error rate threshold for the boundary word line storagecell 302. For instance, the trigger detection component 502 may detect ahigh (e.g., above a threshold), abnormal, and/or the like rate oferrors, e.g., read errors detected during read operations performed onboundary word line storage cells 302, which may indicate that thevoltage setting for reading data from the boundary word line storagecell 302 is not optimal, and thus the read voltage threshold and/or theread voltage threshold shift for the boundary word line storage cell 302should be calibrated/recalibrated.

In further embodiments, the trigger condition includes determining thata temperature associated with a boundary word line storage cell 302satisfies a temperature threshold for the boundary word line storagecell 302. In certain embodiments, the temperature of the non-volatilestorage device that includes the boundary word line storage cells 302may vary and change on an ongoing basis from less than a degree to asmuch as a few degrees or more. Accordingly, the temperature changes mayaffect the read voltage thresholds for the boundary word line storagecells 302 differently than other programmed storage cells in the eraseblock.

In such an embodiment, the voltage determination component 150, acontroller 126, and/or the like may track, monitor, check, or the likethe temperature of the boundary word line storage cells 302, thetemperature of the erase block, the temperature of the die 212, dieplane, storage device, and/or the like. If the temperature satisfies thetemperature threshold, e.g., the temperature is greater than, less than,and/or equal to the temperature threshold, the voltage determinationcomponent 150, a controller 126, and/or the like may notify or signalthe trigger detection component 502 that the temperature threshold hasbeen satisfied.

In one embodiment, the trigger condition includes determining that anumber of read operations that are performed on a boundary word linestorage cell 302 satisfies, e.g., is greater than or equal to, apredetermined read operation threshold for the boundary word linestorage cell 302. For example, the voltage determination component 150,a controller 126, and/or the like may track how many read operations areperformed on boundary word line storage cells 302, and may notify orsignal the trigger detection component 502 when the number of detectedread operations is greater than or equal to a threshold number of readoperations.

The trigger detection component 502 may detect or monitor for othertrigger conditions or factors including a number of program/erase(“P/E”) cycles for the erase block, the location in the memory array ofboundary word line storage cells 302, the number of uncorrectable errorsdetected on a boundary word line storage cell 302, the data retentiontimes for boundary word line storage cells 302, and/or the like. Forexample, if the P/E cycle count for the erase block is greater than orequal to a predetermined P/E cycle count threshold, then the triggerdetection component 502 may signal that recalibration of the voltageshifts of the boundary word line storage cells 302 should be performed.Similarly, if a boundary word line storage cell 302 has stored data foran amount of time that exceeds a predetermined retention threshold time,then the trigger detection component 502 may signal that recalibrationof the voltage shifts of the boundary word line storage cells 302 shouldbe performed.

In certain embodiments, after the trigger detection component 502detects the trigger condition, the trigger detection component 502notifies, signals, and/or the like the voltage component 504 and/or thevoltage shift component 506 to initiate calibration/recalibration of theread voltage threshold shift for the boundary word lines 302.

In one embodiment, the voltage component 504 is configured todynamically determine a read voltage threshold for a boundary word linestorage cell 302 of a partially programmed erase block in response tothe trigger condition that the trigger detection component 502 detects.To determine the read voltage threshold for a boundary word line storagecell 302, in one embodiment, the voltage component 504 reads data fromthe boundary word line storage cell 302 using a predefined,predetermined, default, set, stored, configured, and/or the like readvoltage threshold. In certain embodiments, the read voltage thresholdthat the voltage component 504 uses to read data from the boundary wordline storage cell 302 is different than a default read voltage thresholdfor the boundary word line storage cell 302.

For instance, in one embodiment, the voltage component 504 reads datafrom a boundary word line storage cell 302 using a default read voltagethreshold, e.g., a read voltage threshold that is set by themanufacturer, storage controller 126, and/or the like. In anotherembodiment, the voltage component 504 reads data from a boundary wordline storage cell 302 using a read voltage threshold that is determineddynamically while the non-volatile memory device 120 is in use. Forexample, the voltage component 504 may reference a table of read voltageshifts for the boundary word line storage cell 302 and use the defaultor other reference read voltage threshold adjusted by the read voltageshift for the particular boundary word line storage cell 302 to readdata from the boundary word line storage cell 302. In some embodiments,as discussed above, the read voltage shift may be a static, predefined,predetermined value that does not change dynamically over time as thenon-volatile memory device 120 is in use. Accordingly, using the fixedread voltage shift may not be the optimal read voltage threshold for theboundary word line storage cell 302.

In one embodiment, to determine the optimal read voltage threshold for aboundary word line storage cell 302, the voltage component 504 readsdata from the boundary word line storage cell 302 using a read voltagethreshold for the boundary word line storage cell 302 and uses an errorcorrection code (“ECC”) word to locate, determine, find, and/or the likethe boundary between states or abodes for the boundary word line storagecell 302. For example, a single-level memory cell may have two states, ahigh and a low state, that can be read using a read voltage thresholdrange that corresponds to the states. Over time the read voltagethreshold range may shift up or down based on various factors, asdiscussed above, such as read disturbs, program disturbs, temperature,and/or the like. Boundary word line storage cells 302, however, may havedifferent read voltage threshold characteristics due to their locationin the erase block, e.g., adjacent to a programmed storage cell and anunprogrammed storage cell, than other programmed storage cells in anerase block. Thus, the optimal read voltage threshold for a boundaryword line storage cell 302 may be different than other programmedstorage cells. Accordingly, predefined or static voltage shifts oradjustments may not apply to boundary word line storage cells 302 likeit does to other programmed storage cells in the erase block. Therefore,in one embodiment, the voltage component 504 uses a read voltagethreshold and an ECC code word to determine the optimal read voltagethresholds for a boundary word line storage cell 302.

The voltage shift component 506, in one embodiment, is configured todynamically calculate a read voltage threshold shift for a boundary wordline storage cell 302 based on the read voltage threshold that thevoltage component 504 determined for the boundary word line storage cell302 and a baseline read voltage threshold. The baseline read voltagethreshold, for example, may include a default read voltage threshold, apredefined read voltage threshold, a calculated, estimated, or otherwisedynamically determined read voltage threshold, and/or the like for theNAND string 301, the erase block, the die 212, the die plane, thenon-volatile storage device 120, and/or the like. Determination of thebaseline read voltage threshold is described in more detail below withreference to the baseline voltage component 604.

In one embodiment, the voltage shift component 506 determines orcalculates the read voltage threshold shift for a boundary word linestorage cell 302 as a function of the baseline read voltage threshold,e.g., by taking the difference between the read voltage threshold forthe boundary word line 302 and the baseline read voltage, by calculatingan average read voltage threshold using the read voltage threshold forthe boundary word line 302 and the baseline read voltage and determiningthe difference between the average read voltage threshold and the readvoltage threshold for the boundary word line 302, and/or the like. Incertain embodiments, the read voltage threshold shift determined as afunction of the baseline read voltage threshold that the voltage shiftcomponent 506 determines is stored for future reference in a table, adata store, a list, a log, and/or the like, as explained in more detailbelow.

FIG. 6 is a schematic block diagram illustrating one embodiment of avoltage determination component 150 for dynamically determining boundaryword line voltage shift. The voltage determination component 150, in oneembodiment, includes one or more of a trigger detection component 502, avoltage component 504, and a voltage shift component 506, which may besubstantially similar to the trigger detection component 502, thevoltage component 504, and the voltage shift component 506 describedabove with reference to FIG. 6. In further embodiments, the voltagedetermination component 150 includes one or more of a thresholdcomponent 602, a baseline voltage component 604, and a reference tablecomponent 606, which are described in more detail below.

The threshold component 602, in one embodiment, is configured todetermine thresholds for detecting the trigger condition for a boundaryword line storage cell 302. In certain embodiments, the thresholds mayinclude thresholds for an amount of time since the read voltagethreshold for the boundary word line storage cell 302 was lastcalculated, temperature thresholds, data retention time thresholds, P/Ecycle count thresholds, error/error rate thresholds, read operationcount thresholds, program operation count thresholds, and/or the like.In various embodiments, the threshold component 602 determines thethresholds according to the location of the boundary word line storagecell 302, e.g., the position in the NAND string 301, the position in theerase block, the position in the die 212, and/or the like.

For example, the threshold component 602 may determine that the locationof a boundary word line storage cell 302 in a 3D NAND string is morereactive, sensitive, responsive, and/or the like to temperature andtherefore may set a low temperature threshold for the triggerdetermination component 502 to monitor so that small temperature changesmay trigger the recalibration of the read voltage threshold shift forthe boundary word line storage cell 302. Similarly, if the location of aboundary word line storage cell 302 in a 3D NAND string is lessreactive, sensitive, responsive, and/or the like to temperature, thethreshold component 602 may set a high temperature threshold for thetrigger determination component 502 to monitor so that largertemperature changes may trigger the recalibration of the read voltagethreshold shift for the boundary word line storage cell 302.

In one embodiment, the baseline voltage component 604 is configured todetermine a baseline read voltage threshold for a boundary word linestorage cell 302, a NAND string, an erase block, a die 212, anon-volatile storage device 120, and/or the like. In one embodiment, thebaseline voltage component 604 references a predetermined, predefined,preset, and/or the like read voltage threshold for one or more referencestorage cells for the erase block, e.g., storage cells that have beendesignated as storage cells that have an optimal read voltage thresholdand/or other storage cells that are programmed and are not boundary wordline storage cells 302 for the NAND string 301, the erase block, the die212, the die plane, the non-volatile storage device 120, and/or thelike. Furthermore, the voltage shift component 506 may furtherincorporate any predetermined voltage shifts, e.g., by referencing avoltage shift threshold for the sample storage cells. For example, forthe particular sampled storage cells, the determined voltage may beshifted

In one embodiment, the voltage shift component 506 dynamicallydetermines or calculates the baseline read voltage threshold by samplingread voltage thresholds for one or more programmed storage cells of thepartially programmed erase block where the boundary word line storagecells 302 are located, of a corresponding fully-programmed erase block,of other erase blocks that are partially or fully programmed, of otherdies 212, of other non-volatile storage devices 120, and/or the like.For example, the voltage shift component 506 may calculate or determinethe baseline voltage dynamically in response to the trigger detectioncomponent 502 detecting the trigger condition by sampling read voltagethresholds for one or more programmed storage cells of the partiallyprogrammed erase block. The voltage shift component 506 may use amedian, mode, mean, and/or the like of the sampled read voltagethresholds as the baseline read voltage threshold.

In one embodiment, the reference table component 606 is configured togenerate one or more reference tables of calculated voltage shifts forboundary word line storage cells 302. The reference tables, forinstance, may be referenced to determine the read voltage shift forboundary word line storage cells 302 when read operations are performedon boundary word line storage cells 302. The reference table, in oneembodiment, includes a database table, a list, a log, a map (e.g., amapping of boundary word line storage cells 302 to read voltage shiftscorresponding to the boundary word line storage cells 302), and/or thelike. In certain embodiments, the reference table component 606 storesthe reference tables in volatile memory such as SRAM, DRAM, and/or thelike of a controller 126. In some embodiments, the reference tablecomponent 606 stores the reference tables in non-volatile memory, suchas on the non-volatile storage device 120, so that the reference tablespersist across power cycles of the host computing device 110.

In one embodiment, the reference table component 606 creates separatereference tables for each boundary word line storage cell 302. In suchan embodiment, each reference table may comprise a single read voltagethreshold shift for a corresponding boundary word line storage cell 302.This may otherwise be known as creating a reference table on a per NANDstring 301 basis because each NAND string 301 may have only one boundaryword line storage cell 302.

In further embodiments, the reference table component 606 createsreference tables for multiple NAND strings 301 or groups of NAND Strings301 such that the read voltage threshold shift stored in the referencetable corresponds to multiple boundary word line storage cells 302.Similarly, the reference table component 606 creates reference tablesfor each NAND string 301 in an erase block such that the read voltagethreshold shift stored in the reference table corresponds to eachboundary word line storage cell 302 of each NAND string 301 in the eraseblock. In certain embodiments, the reference table component 606 createsa reference table for multiple erase blocks, multiple dies 212, and/orthe like such that the read voltage threshold shift corresponds to eachboundary word line storage cell 302 of each of the multiple eraseblocks. In such an embodiment, the erase blocks, dies 212, and/or thelike may have similar storage characteristics for boundary word linestorage cells 302 such as substantially similar read counts, P/E counts,temperatures, data retention times, and/or the like.

In one embodiment, the reference table component 606 also include thedetermined read voltage threshold for a boundary word line storage cell302 in the reference table so that the determined read voltage thresholdcan be used for read operations instead of, or in addition to, thedetermined read voltage threshold shift.

FIG. 7 is a schematic flow chart diagram illustrating one embodiment ofa method for dynamically determining boundary word line voltage shift.In one embodiment, the method 700 begins and the trigger determinationcomponent 502 detects 702 a trigger condition associated with a boundaryword line storage cell 302 (a.k.a., a last programmed word line) of apartially programmed erase block. In further embodiments, the voltagecomponent 504 determines 704 a read voltage threshold for the boundaryword line storage cell 302 of the partially programmed erase block inresponse to the trigger condition. In certain embodiments, the voltageshift component 506 dynamically calculates 706 a read voltage thresholdshift for the boundary word line storage cell 302 based on thedetermined read voltage threshold for the boundary word line storagecell 302 and a baseline read voltage threshold, and the method 700 ends.

FIG. 8 is a schematic flow chart diagram illustrating one embodiment ofa method for dynamically determining boundary word line voltage shift.In one embodiment, the method 800 begins and the trigger determinationcomponent 502 detects 802 a trigger condition associated with a boundaryword line storage cell 302 (a.k.a., a last programmed word line) of apartially programmed erase block. In further embodiments, the voltagecomponent 504 determines 804 a read voltage threshold for the boundaryword line storage cell 302 of the partially programmed erase block inresponse to the trigger condition.

In one embodiment, the baseline voltage component 604 determines 806 abaseline read voltage threshold. In some embodiments, the voltage shiftcomponent 506 dynamically calculates 808 a read voltage threshold shiftfor the boundary word line storage cell 302 based on the determined readvoltage threshold for the boundary word line storage cell 302 and abaseline read voltage threshold. In various embodiments, the referencetable component 606 generates 810 a reference table for the calculatedread voltage threshold shift, and the method 800 ends.

Means for detecting a trigger condition associated with a lastprogrammed word line (a boundary word line storage cell 302) includes,in various embodiments, may include one or more of a voltagedetermination component 150, a trigger determination component 502, acontroller 126, a die controller 220, a non-volatile memory deviceinterface 139, a host computing device 110, a device driver, acontroller (e.g., a device driver, or the like) executing on a hostcomputing device 110, a processor 111, an FPGA, an ASIC, other logichardware, and/or other executable code stored on a computer-readablestorage medium. Other embodiments may include similar or equivalentmeans for detecting a trigger condition associated with a lastprogrammed word line (a boundary word line storage cell 302).

Means for determining a read voltage threshold for a last programmedword line (a boundary word line storage cell 302) of a partiallyprogrammed erase block in response to a trigger condition include, invarious embodiments, may include one or more of a voltage determinationcomponent 150, a voltage component 504, a controller 126, a diecontroller 220, a non-volatile memory device interface 139, a hostcomputing device 110, a device driver, a controller (e.g., a devicedriver, or the like) executing on a host computing device 110, aprocessor 111, an FPGA, an ASIC, other logic hardware, and/or otherexecutable code stored on a computer-readable storage medium. Otherembodiments may include similar or equivalent means for determining aread voltage threshold for a last programmed word line (a boundary wordline storage cell 302) of a partially programmed erase block in responseto a trigger condition.

Means for calculating, dynamically, a read voltage threshold shift for alast programmed word line (e.g., a boundary word line storage cell 302)based on a determined read voltage threshold for the last programmedword line (e.g., the boundary word line storage cell 302) and a baselineread voltage threshold include, in various embodiments, may include oneor more of a voltage determination component 150, a voltage shiftcomponent 506, a controller 126, a die controller 220, a non-volatilememory device interface 139, a host computing device 110, a devicedriver, a controller (e.g., a device driver, or the like) executing on ahost computing device 110, a processor 111, an FPGA, an ASIC, otherlogic hardware, and/or other executable code stored on acomputer-readable storage medium. Other embodiments may include similaror equivalent means for calculating, dynamically, a read voltagethreshold shift for the last programmed word line (a boundary word linestorage cell 302) based on the determined read voltage threshold for thelast programmed word line (the boundary word line storage cell 302) anda baseline read voltage threshold.

Means for reading data from a last programmed word line based on a readvoltage threshold shift for the last programmed word line, in variousembodiments, may include one or more of a sense amplifier 250, a voltagedetermination component 150, a voltage shift component 506, a controller126, a die controller 220, a non-volatile memory device interface 139, ahost computing device 110, a device driver, a controller (e.g., a devicedriver, or the like) executing on a host computing device 110, aprocessor 111, an FPGA, an ASIC, other logic hardware, and/or otherexecutable code stored on a computer-readable storage medium. Otherembodiments may include similar or equivalent means for reading datafrom a last programmed word line based on a read voltage threshold shiftfor the last programmed word line.

The embodiments may be practiced in other specific forms. The describedembodiments are to be considered in all respects only as illustrativeand not restrictive. The scope of the invention is, therefore, indicatedby the appended claims rather than by the foregoing description. Allchanges which come within the meaning and range of equivalency of theclaims are to be embraced within their scope.

The present disclosure may be embodied in other specific forms withoutdeparting from its spirit or essential characteristics. The describedembodiments are to be considered in all respects only as illustrativeand not restrictive. The scope of the disclosure is, therefore,indicated by the appended claims rather than by the foregoingdescription. All changes that come within the meaning and range ofequivalency of the claims are to be embraced within their scope.

What is claimed is:
 1. An apparatus comprising: an array of non-volatilememory cells; and a controller configured to: detect a trigger conditionassociated with a last programmed word line of a partially programmederase block of the array of non-volatile memory cells, the lastprogrammed word line comprising programmed non-volatile memory cellsthat are adjacent to programmed non-volatile memory cells andunprogrammed non-volatile memory cells of the array, the triggercondition comprising detecting that a predetermined amount of time haspassed since the read voltage threshold shift for the last programmedword line was determined; determine a read voltage threshold only foruse with the last programmed word line of the partially programmed eraseblock in response to the trigger condition; and calculate, dynamically,a read voltage threshold shift only for use with the last programmedword line based on the determined read voltage threshold for the lastprogrammed word line and a baseline read voltage threshold.
 2. Theapparatus of claim 1, wherein the trigger condition comprisesdetermining that an error rate for the last programmed word linesatisfies a predetermined error rate threshold for the last programmedword line.
 3. The apparatus of claim 1, wherein the trigger conditioncomprises determining that a temperature associated with the lastprogrammed word line satisfies a predetermined temperature threshold forthe last programmed word line.
 4. The apparatus of claim 1, wherein thetrigger condition comprises determining that a number of read operationsperformed on the last programmed word line satisfies a predeterminedread operation threshold for the last programmed word line.
 5. Theapparatus of claim 1, wherein the controller is further configured todetermine the read voltage threshold for the last programmed word lineby: reading data from the last programmed word line using a first readvoltage threshold, the first read voltage threshold different than adefault read voltage threshold for the last programmed word line; andadjusting the first read voltage threshold using one or more errorcorrection code words to determine the boundary between states for thelast programmed word line, the determined read voltage thresholdcomprising the read voltage threshold at the boundary.
 6. The apparatusof claim 1, wherein the controller is further configured to: determine astring position of a memory cell comprising the last programmed wordline; and determine thresholds for detecting the trigger condition forthe last programmed word line based on the determined string position ofthe memory cell.
 7. The apparatus of claim 1, wherein the controller isfurther configured to determine the baseline read voltage threshold byreferencing predetermined read voltage thresholds of one or moreprogrammed memory cells that do not comprise the last programmed wordline.
 8. The apparatus of claim 1, wherein the controller is furtherconfigured to determine the baseline read voltage threshold by sampling,dynamically, read voltage thresholds of one or more programmed memorycells of the partially programmed erase block.
 9. The apparatus of claim1, wherein the controller is further configured to determine thebaseline read voltage threshold by sampling, dynamically, read voltagethresholds of one or more programmed memory cells of a correspondingfully-programmed erase block.
 10. The apparatus of claim 1, wherein thecontroller is further configured to generate one or more referencetables of calculated voltage shifts, the one or more reference tablescomprising voltage shifts for last programmed word lines of one or moreof: a string of memory cells; a group of strings of memory cells; anerase block; and a group of erase blocks.
 11. The apparatus of claim 10,wherein the controller is further configured to include the determinedread voltage thresholds for the last programmed word line in the one ormore reference tables.
 12. The apparatus of claim 1, wherein the arrayof non-volatile memory cells comprises vertical strings of memory cellsof a 3D NAND flash memory device.
 13. A method comprising: determining aread voltage threshold only for use with a last programmed word line ofa partially programmed erase block of an array of non-volatile memorycells in response to detecting a trigger condition associated with thelast programmed word line, the last programmed word line comprisingprogrammed non-volatile memory cells that are adjacent to programmednon-volatile memory cells and unprogrammed non-volatile memory cells ofthe array; determining a baseline read voltage threshold by one or moreof: referencing predetermined read voltage thresholds of one or moreprogrammed memory cells that do not comprise the last programmed wordline; sampling, dynamically, read voltage thresholds of one or moreprogrammed memory cells of the partially programmed erase block; andsampling, dynamically, read voltage thresholds of one or more programmedmemory cells of a corresponding fully-programmed erase block;calculating, dynamically, a read voltage threshold shift only for usewith the last programmed word line based on the determined read voltagethreshold for the last programmed word line and the baseline readvoltage threshold; and reading data from the last programmed word lineusing the determined read voltage threshold based on the read voltagethreshold shift.
 14. The method of claim 13, wherein the triggercondition comprises one or more of: detecting that a predeterminedamount of time has passed since the read voltage threshold shift for thelast programmed word line was determined; determining that an error ratefor the last programmed word line satisfies a predetermined error ratethreshold for the last programmed word line; determining that atemperature associated with the last programmed word line satisfies apredetermined temperature threshold for the last programmed word line;and determining that a number of read operations performed on the lastprogrammed word line satisfies a predetermined read operation thresholdfor the last programmed word line.
 15. The method of claim 13, furthercomprising determining the read voltage threshold for the lastprogrammed word line by: reading data from the last programmed word lineusing a first read voltage threshold, the first read voltage thresholddifferent than a default read voltage threshold for the last programmedword line; and adjusting the first read voltage threshold using one ormore error correction code words to determine the boundary betweenstates for the last programmed word line, the determined read voltagethreshold comprising the read voltage threshold at the boundary.
 16. Themethod of claim 13, further comprising: determining a string position ofa memory cell comprising the last programmed word line; and determiningthresholds for detecting the trigger condition for the last programmedword line based on the determined string position of the memory cell.17. The method of claim 13, further comprising generating one or morereference tables of calculated voltage shifts, the one or more referencetables comprising voltage shifts for last programmed word lines of oneor more of: a string of memory cells; a group of strings of memorycells; an erase block; and a group of erase blocks.
 18. An apparatuscomprising: means for detecting a trigger condition associated with alast programmed word line of a partially programmed erase block of anarray of non-volatile memory cells, the last programmed word linecomprising programmed non-volatile memory cells that are adjacent toprogrammed non-volatile memory cells and unprogrammed non-volatilememory cells of the array, the trigger condition comprising detectingthat a predetermined amount of time has passed since the read voltagethreshold shift for the last programmed word line was determined; meansfor determining a read voltage threshold only for use with the lastprogrammed word line of the partially programmed erase block in responseto the trigger condition; mean for calculating, dynamically, a readvoltage threshold shift only for use with the last programmed word linebased on the determined read voltage threshold for the last programmedword line and a baseline read voltage threshold; and means for readingdata from the last programmed word line based on the read voltagethreshold shift for the last programmed word line.
 19. The apparatus ofclaim 18, further comprising means for determining a baseline readvoltage threshold by one or more of: referencing predetermined readvoltage thresholds of one or more programmed memory cells that do notcomprise the last programmed word line; sampling, dynamically, readvoltage thresholds of one or more programmed memory cells of thepartially programmed erase block; and sampling, dynamically, readvoltage thresholds of one or more programmed memory cells of acorresponding fully-programmed erase block.
 20. A method, comprising:determining a string position of a memory cell comprising a lastprogrammed word line of a partially programmed erase block of an arrayof non-volatile memory cells, the last programmed word line comprisingprogrammed non-volatile memory cells that are adjacent to programmednon-volatile memory cells and unprogrammed non-volatile memory cells ofthe array; determining thresholds for detecting a trigger condition forthe last programmed word line based on the determined string position ofthe memory cell; determining a read voltage threshold only for use withthe last programmed word line in response to detecting a triggercondition, based on the determined thresholds, associated with the lastprogrammed word line; calculating, dynamically, a read voltage thresholdshift only for use with the last programmed word line based on thedetermined read voltage threshold for the last programmed word line anda baseline read voltage threshold; and reading data from the lastprogrammed word line using the determined read voltage threshold basedon the read voltage threshold shift.